作者在 2009-02-17 13:56:50 发布以下内容
// PAGE 0--3
#define CR reg00 // Command Register
#define CR reg00 // Command Register
// PAGE 0 [R]
#define CLDA0 reg01 // Current Local DMA Register 0
#define CLDA1 reg02 //
#define BNRY reg03 //
#define TSR reg04 // Transmit Status Register
#define NCR reg05 // Number of Collisions Register
#define FIFO reg06 // First In Fisrt Out Register
#define ISR reg07 //
#define CRDA0 reg08 // Current Remote DMA Register 0
#define CRDA1 reg09 //
//#define 8019ID0 reg0A //
//#define 8019ID1 reg0B //
#define RSR reg0C // Receive Status Register
#define CNTR0 reg0D // Frame Alignment Error Tally Counter Register
#define CNTR1 reg0E // CRC Error Tally Counter Register
#define CNTR2 reg0F // Missed Packed Tally Counter Register
#define CLDA0 reg01 // Current Local DMA Register 0
#define CLDA1 reg02 //
#define BNRY reg03 //
#define TSR reg04 // Transmit Status Register
#define NCR reg05 // Number of Collisions Register
#define FIFO reg06 // First In Fisrt Out Register
#define ISR reg07 //
#define CRDA0 reg08 // Current Remote DMA Register 0
#define CRDA1 reg09 //
//#define 8019ID0 reg0A //
//#define 8019ID1 reg0B //
#define RSR reg0C // Receive Status Register
#define CNTR0 reg0D // Frame Alignment Error Tally Counter Register
#define CNTR1 reg0E // CRC Error Tally Counter Register
#define CNTR2 reg0F // Missed Packed Tally Counter Register
// PAGE 0 [W]
#define PSTART reg01 // Page Start Register
#define PSTOP reg02 // Page Stop Register
#define BNRY reg03 // Boundary Register
#define TPSR reg04 // Transmit Page Start Register
#define TBCR0 reg05 // Transmit Byte Count Register 0
#define TBCR1 reg06 //
#define ISR reg07 //
#define RSAR0 reg08 //
#define RSAR1 reg09 //
#define RBCR0 reg0A // Remote Byte Count Register 0
#define RBCR1 reg0B //
#define RCR reg0C // Receive Configuration Register
#define TCR reg0D // Transmit Configuration Register
#define DCR reg0E // Data Configuration Register
#define IMR reg0F // Interrupt Mask Register
#define PSTART reg01 // Page Start Register
#define PSTOP reg02 // Page Stop Register
#define BNRY reg03 // Boundary Register
#define TPSR reg04 // Transmit Page Start Register
#define TBCR0 reg05 // Transmit Byte Count Register 0
#define TBCR1 reg06 //
#define ISR reg07 //
#define RSAR0 reg08 //
#define RSAR1 reg09 //
#define RBCR0 reg0A // Remote Byte Count Register 0
#define RBCR1 reg0B //
#define RCR reg0C // Receive Configuration Register
#define TCR reg0D // Transmit Configuration Register
#define DCR reg0E // Data Configuration Register
#define IMR reg0F // Interrupt Mask Register
// PAGE 1 [R/W]
#define PAR0 reg01 // Physical Address Register
#define PAR1 reg02 //
#define PAR2 reg03 //
#define PAR3 reg04 //
#define PAR4 reg05 //
#define PAR5 reg06 //
#define CURR reg07 // Current Page Register
#define MAR0 reg08 // Multicast Address Register
#define MAR1 reg09 //
#define MAR2 reg0A //
#define MAR3 reg0B //
#define MAR4 reg0C //
#define MAR5 reg0D //
#define MAR6 reg0E //
#define MAR7 reg0F //
#define PAR0 reg01 // Physical Address Register
#define PAR1 reg02 //
#define PAR2 reg03 //
#define PAR3 reg04 //
#define PAR4 reg05 //
#define PAR5 reg06 //
#define CURR reg07 // Current Page Register
#define MAR0 reg08 // Multicast Address Register
#define MAR1 reg09 //
#define MAR2 reg0A //
#define MAR3 reg0B //
#define MAR4 reg0C //
#define MAR5 reg0D //
#define MAR6 reg0E //
#define MAR7 reg0F //
// PAGE 2 [R]
#define PSTART reg01 //
#define PSTOP reg02 //
#define TPSR reg04 //
#define RCR reg0C //
#define TCR reg0D //
#define DCR reg0E //
#define IMR reg0F //
#define PSTART reg01 //
#define PSTOP reg02 //
#define TPSR reg04 //
#define RCR reg0C //
#define TCR reg0D //
#define DCR reg0E //
#define IMR reg0F //